The present specification relates generally to integrated circuit (IC) fabrication. More particularly, the present specification relates to fabrication of IC features having sub-lithographic lateral dimensions using a preferentially hardened etch resistant photoresist surface.
The semiconductor or integrated circuit (IC) industry aims to manufacture ICs with higher and higher densities of devices on a smaller chip area to achieve greater functionality and to reduce manufacturing costs. This desire for large scale integration requires continued shrinking of circuit dimensions and device features. The ability to reduce the size of structures, such as, gate lengths in field-effect transistors and the width of conductive lines, is driven by lithographic performance.
IC fabrication techniques often utilize a photomask (also referred to as a mask) or a reticle. Radiation is provided selectively through or reflected off the mask or reticle to form an image on a semiconductor wafer. Generally, the image is projected and patterned onto a layer of material, such as, photoresist material, on the wafer. In turn, the patterned photoresist material is utilized to define doping regions, deposition regions, etching regions, and/or other structures of the IC. The patterned photoresist material can also define conductive lines or conductive pads associated with metal layers of the IC. Further, the patterned photoresist material can define isolation regions, transistor gates, or other device structures and elements.
To transfer an image or pattern onto the photoresist material, lithography systems include a light source configured to provide electromagnetic radiation or light at one or more wavelengths. The light source may produce radiation at a wavelength of 365 nanometers (nm), 248 nm, and/or 193 nm. The photoresist material patterned by such radiation is selected to be responsive to the wavelength of such radiation. Preferably, the areas of the photoresist material upon which radiation is incident undergo a photochemical change such that it becomes suitably soluble or insoluble in a subsequent developing step.
As IC device dimensions continue to shrink, it becomes necessary to define dimensions that are smaller than what is possible using conventional lithographic techniques. One process for achieving sub-lithographic device dimensions is by reducing or xe2x80x9ctrimmingxe2x80x9d features defined on the patterned photoresist material before such features are patterned onto the underlying layer(s). This process, commonly referred to as a resist trim or trimming process, utilizes a plasma etch to remove some of the patterned photoresist material such that the lateral dimensions of the trimmed features will be smaller than the original lithographically patterned features (i.e., before the trimming process).
In a resist trimming process, the plasma bombards all surfaces of the patterned photoresist material, such that top surface as well as side or lateral surfaces of the patterned photoresist material are ashed. Hence, as the trimming time is increased (i.e., the patterned photoresist material is exposed to the plasma etch for a longer period of time) in order to further reduce lateral dimensions (i.e., further ash the side surfaces, thereby reducing the width of features, such as, contact lines), the thickness of the patterned photoresist material is also being reduced (due to erosion of its top surface). Unfortunately, with enough thinning of the patterned photoresist material, there may not be enough photoresist thickness remaining to survive or with which to perform subsequent processes, such as pattern transfer to underlying layer(s) via an etch process.
Moreover, in some cases, the plasma has a tendency to bombard the top surface of the patterned photoresist material more than the lateral surfaces. As such, in an aggressive trimming process with a layer of photoresist material having a starting thickness of 300 nm, by the time approximately 50 nm has been trimmed from all sides of a given feature, in other words, achieving a 100 nm lateral reduction, close to 100 nm of vertical thickness may also be lost. This amount of thinning of the photoresist material is likely to result in pattern destruction during subsequent processes.
To combat the photoresist thinning problem, thicker layers of photoresist material have been considered to combat resist thinning that occurs during the trimming process. However, thicker layers of photoresist material are susceptible to pattern deformation and/or incomplete pattern transfer on the photoresist material become issues. Because the resolution of features is, in part, proportional to the inverse of the exposure or lithographic wavelength, it is desirable to pattern photoresist material using shorter exposure wavelengths (e.g., 157 nm, 126 nm, or 13.4 nm). Presently, no photoresist materials exist that are specifically suited for such shorter exposure wavelengths. Hence, photoresist materials conventionally used in 265 nm, 248 nm, or 193 nm lithography are utilized, even for the shorter exposure wavelengths.
The longer wavelength photoresist materials exhibit high optical absorption per unit thickness at the shorter exposure wavelengths. The longer wavelength photoresist materials are increasingly opaque to shorter wavelength radiation and the necessary photochemical change does not occur throughout the entire thickness of the material. As the photoresist material thickness is increased, incomplete pattern transfer throughout the entire thickness of the material is even more likely to occur.
Alternatively, even if complete pattern transfer has occurred, prolonged trimming (to achieve very narrow features in the thicker patterned photoresist material) can cause pattern deformation, such as, pattern collapse, pattern bending, or pattern breakage. The probability of pattern deformation of a given feature increases as its aspect ratio (i.e., the ratio of the height vs. the width of the feature), increases. Thus, a thicker photoresist material is more likely to result in pattern deformation.
Using a conventional thickness of photoresist material places a limit on lateral trimming due to vertical consumption concerns. Namely, since the ashing process also thins the photoresist as it narrows the patterned features, the trimming process must be stopped before desirable lateral reduction has been achieved to ensure that a thick enough layer of patterned photoresist material remains for subsequent processes (e.g., etch processes for pattern transfer to underlying layer(s), such as a polysilicon gate formation). On the other hand, starting with a thicker layer of photoresist material to permit prolonged trimming is also problematic due to incomplete pattern transfer and/or pattern deformation concerns.
Thus, there is a need for a process for permitting a conventional photoresist trimming process to be utilized to its maximum potential. There is a further need for a process for laterally trimming patterned features on a photoresist material without such photoresist material having associated therewith pattern deformation, incomplete pattern transfer, or insufficient vertical thickness for subsequent lithographic processes. Even further still, there is a need for a process for forming sub-lithographic photoresist features without extensive modification to conventional lithographic techniques, tools, materials, or equipment or significantly decreasing throughout.
One exemplary embodiment relates to a method of trimming a feature patterned on a photoresist layer. The photoresist layer is disposed over a substrate and the feature includes a top portion and lateral surfaces. The method includes modifying the top portion of the feature patterned on the photoresist layer in an ion-dominated environment to form a modified top portion. The method further includes trimming the feature patterned on the photoresist layer to form a trimmed feature. A vertical trim rate and a lateral trim rate are associated with the feature. The vertical trim rate is slower than the lateral trim rate due to the modified top portion.
Another exemplary embodiment relates to an integrated circuit fabrication process. The process includes developing a patterned photoresist layer, and modifying the patterned photoresist layer to form a top portion and a bottom portion of the at least one feature. The patterned photoresist layer includes at least one feature. The top portion has a top etch rate and the bottom portion has a bottom etch rate. The top etch rate is different from the bottom etch rate. The process further includes trimming the patterned photoresist layer to change the at least one feature to have a sub-lithographic lateral dimension and a sufficient vertical thickness to maintain pattern integrity. The modifying step is performed after the developing step and before the ashing step.
Still another exemplary embodiment relates to an integrated circuit having a feature of sub-lithographic dimension. The feature is formed by the process including patterning the feature on a photoresist layer disposed over a substrate, developing the feature patterned on the photoresist layer, and changing at least a portion of the photoresist layer. The feature is patterned in accordance with a radiation at a lithographic wavelength and a pattern provided on a mask or a reticle. A top portion of the feature patterned on the photoresist layer is changed to have a different etch rate from a bottom portion of the feature patterned on the photoresist layer. The process further includes trimming the feature patterned on the photoresist layer to a sub-lithographic dimension, and transferring the trimmed feature patterned on the photoresist layer to the substrate. The feature in the substrate has the sub-lithographic dimension.